Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data and includes random-access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can provide persistent data by retaining stored information when not powered and can include NAND flash memory, NOR flash memory, read only memory (ROM), Electrically Erasable Programmable ROM (EEPROM), Erasable Programmable ROM (EPROM), and phase change random access memory (PCRAM), among others.
Various types of memory can be used in memory systems. For example, Flash memory can be part of a memory system as internal memory or as removable memory that can be coupled to the memory system through an interface via a format such as USB (universal serial bus), MMC (multi media card), CF (compact flash), or SD (secure digital), among others. Flash memory devices, including floating gate flash devices and charge trap flash (CTF) devices, may be utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for sold state drives (SSDs), personal computers, personal digital assistants (PDAs), digital cameras, cellular telephones, portable music players, e.g., MP3 players, and movie players, among others. Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. A NAND array architecture arranges its array of memory cells in a matrix such that the control gates of each memory cell in a “row” of the array are coupled to (and in some cases form) an access line (e.g., a word line as commonly referred to in the art). However each memory cell is not directly coupled to a sense line (e.g., a bit line as commonly referred to in the art) by its drain. Instead, the memory cells of the array are coupled together in series, source to drain, between a common source and a bit line, where the memory cells commonly coupled to a particular bit line are referred to as a “column”.
Sensing operations, such as read operations and program verify operations, can involve providing a potential to a control gate of a selected memory cell and determining whether or not the cell conducts (e.g., based on sensed conduction of the sense line coupled to the selected cell). For MLCs (e.g., memory cells configured to store multiple bits of data), such a sensing operation can require the application of multiple potentials. For example, an MLC capable of being programmed to sixteen states (e.g., a 4-bit cell) can require the application of fifteen different discrete potentials to the control gate to sense the state of the cell. Each potential provided to the control gate is provided for a period of time (e.g., 10 to 20 microseconds), while the sense line carrying the current settles. As such, sensing a 4-bit cell may require the application of fifteen different sensing potentials, which can result can in a 300 microsecond sensing time.
Some sensing operations include the use of a voltage ramp provided to the control gate of the selected cell, rather than discrete sensing voltages. However, such sensing operations can result in erroneous data determinations due to factors such as variations in ramp rate and distortions in ramp value that can occur with process cycling and changing temperature, for example. Also, non-linearity at end portions of the provided ramping voltage, as well as transient effects of the RC (resistor-capacitor) constant associated with word lines and/or bit lines may prevent accurate sensing of the selected cell.